Many integrated circuits increase performance and decrease power requirements by tapping a single, high-speed, synchronous clock into multiple clock domains. In such systems, one or more domains may run at different clock speeds. In the most advanced systems, each individual clock domain is powered by a separate timing clock that can run at a speed independent of all the other timing clocks in the integrated circuit.
An example multiple clock domain integrated circuit 20 is illustrated in FIG. 1. In FIG. 1, the integrated circuit 20 is divided into two clock domains 22 and 26. A clock crossing circuit 24 connects the two domains 22, 26 and manages transferring data between the two domains. Although theoretically an integrated circuit can be divided into any number of separate clock domains, the additional design overhead generally makes having too many domains impractical. With reference to FIG. 1, the clock domain 22 gets its clock signal from a Phase Locked Loop (PLL) 32, while clock domain 26 gets its clock signal from a PLL 36. Each of the PLLs 32, 36 receive a common clock signal 30 from a common reference clock source (not shown) and generates its own clock signal.
There are several problems with this prior art approach. First, even if the PLLs 32, 36 are set to the same frequency, the clock signals driving the clock domains 22 and 26 will not be aligned at the clock edges since the clock reference 30 travels through different paths to the different PLLs 32, 36. To accommodate for this, a skew adjust circuit 34 may be inserted between the PLLs 32, 36. The skew adjust circuit 34 can be adjusted to change the timing of the PLL 36 so that it matches the timing of PLL 32. In this way, the skew adjust circuit 34 can be operated such that the clock domain 22 and clock domain 26 effectively receive their respective clock signals at exactly the same time, regardless of the path the clock signal 30 may take between different PLLs.
In more complex systems where the clock domains 22, 26 operate at different clock frequencies, additional problems arise. One such problem is clock edge misalignment. For instance, if clock domain 22 operates at 4 MHz while clock domain 26 operates at 5 MHz, very few clock edges of both circuits occur simultaneously. With reference to FIG. 2, the two illustrated clock signals only share the same rising edge once per microsecond and their falling edges never align. ID some circuits data can only be transferred at a rising edge of a clock and such data sharing circuits must include large data buffers between them to accommodate for the clock frequency mismatch. This length of the depth/size of the necessary data buffers scales as the operating frequencies between the domains diverge.
In the case of true asynchrony, meta-stable conditions can occur. Metastability issues can never be completely removed, but the probability of failure can be reduced by including extra time to resolve the timing issues. This significantly lowers the maximum transfer rate between clock domains having different clock frequencies.
Embodiments of the invention address these and other limitations in the prior art.